Folded divider architecture

ABSTRACT

A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application patent Ser. No. 15/167,216 filed May 27, 2016, the disclosure of which is incorporated by reference.

TECHNICAL FIELD

This disclosure is related to the field of clock signal generation, and, more particularly, to the generation of multiple clock signals of different frequency and/or duty cycle, from an input clock signal.

BACKGROUND

In the field of electronic devices, such as systems on a chip, a phase lock loop is often used to generate a master clock signal. That master clock signal is then divided downward into a variety of different clock signals for use by different components within the system on chip.

This division is performed by coupling multiple divider circuits to the output of the phase locked loop. For example, a divide by 2, a divide by 4, and a divide by 8 divider circuit are each coupled to the phase locked loop. However, this approach has drawbacks. For example, power consumption may be undesirably high.

It is therefore desirable for new divider circuits to be developed.

SUMMARY

One aspect is directed to a circuit including a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.

Another aspect is directed to a circuit including a counter circuit. The counter circuit includes a clock divider counter configured to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The counter circuit also includes logic configured to compare a value contained in the divider counter to a reference value, and generate an end count signal and increment an end count counter as a function of the value contained in the divider counter matching the reference value. The reference value is set to zero as a function of a least significant bit of the divider value, assertion of a toggle signal, and the end count counter being equal to the odd number signal. The reference value is also set to zero as a function of deassertion of the toggle signal, assertion of a second toggle signal, and the end count counter being equal to a desired fraction. The clock divider counter is also configured to be reloaded with the most significant bits of the divider value as a function of the end count signal.

The circuit also includes a clock divider configured to transition a first toggle signal at a same edge of each pulse of the end count signal, transition a second toggle signal at a same edge of every other pulse of the end count signal, and generate a divided version of the clock signal as a function of the first and second toggle signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an electronic device in accordance with this disclosure.

FIG. 2 is a schematic block diagram of the counter circuit of the divider blocks of FIG. 1 for the case where division by an integer is desired.

FIG. 2A is a timing diagram showing generation of the toggle signal.

FIG. 3 is a schematic block diagram of the clock divider of the divider blocks of FIG. 1 for the case where division by an integer is desired.

FIG. 4 is a flowchart of a method of operation of the counter circuit of FIG. 2.

FIG. 5 is a timing diagram showing operation of a divider block of FIG. 3 while dividing by an odd number.

FIG. 6 is a timing diagram showing operation of a divider block of FIG. 3 while dividing by an even number.

FIG. 7 is a schematic block diagram of the counter circuit of the divider blocks of FIG. 1 for the case where division by a fractional number is desired.

FIG. 8 is a schematic block diagram of the clock divider of the divider blocks of FIG. 1 for the case where division by a fractional number is desired.

FIG. 9 is a flowchart of a method of operation of the counter circuit of FIG. 7.

FIG. 10 is a timing diagram showing operation of a divider of FIG. 8 while dividing by a mixed number having an integer part that is even.

FIG. 11 is a block diagram of a further embodiment of the divider blocks of FIG. 1 for the case where division by a fractional number is desired.

FIG. 12 is a flowchart of a method of generating a divided clock signal in accordance with this disclosure.

FIG. 13 is a timing showing operation of a divider while operating in accordance with the method in the flowchart of FIG. 12.

DETAILED DESCRIPTION

In the following detailed description and the attached drawings and appendices, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced, in some instances, without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present disclosure in unnecessary detail. Additionally, for the most part, specific details, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present disclosure, and are considered to be within the understanding of persons of ordinary skill in the relevant art.

With initial reference to FIG. 1, an electronic device 50 is now described. Here, the electronic device 50 may be a portion of a system on a chip (SOC), for example, which may be incorporated into a portable device, such as a smartphone, tablet, or smartwatch.

The electronic device 50 includes a phase locked loop 52 that outputs a first clock signal, such as a 1 GHz clock signal. A first divider block 54 divides the first clock signal by two, and thus outputs a second clock signal such as a 500 MHz clock signal to each of the divider blocks 56 (DIV1 to DIV6). The divider blocks 56 divide the second clock signal and will now be described with further reference to FIGS. 2-3. It should be appreciated that there may be any number of divider blocks 56 (such as ten or more), that each divider block 56 may divide by a different amount, and that some divider blocks 56 may divide by integer numbers while other divider blocks may divide by fractional numbers.

Each divider block 56 includes a counter circuit 100 that includes a divider counter store 102 to store a number (Divider value) by which that divider block 56 is to divide second clock signal, and a clock divider counter 104. The clock divider counter 104 is loaded with the most significant bits of the number in the divider counter store 102 when enabled by output from the OR gate 106.

An AND gate 108 receives as input the least significant bit of the divider counter store 102 and a toggle signal, and provides an output that is then inverted and fed to an input of a

NOR gate 110, and fed to an input of a NOR gate 112 in uninverted form. Each bit held in the divider counter 104 is fed to other inputs of the NOR gate 110, as well as the NOR gate 112, with the least significant bit being inverted prior to being fed to the input of the NOR gate 112. Outputs from the NOR gates 110 and 112 are fed as inputs to the OR gate 114, which assert an end count signal (End_count), which is fed as input to the OR gate 106 together with a load signal.

Operation of the counter circuit 100 will now be described with additional reference to the flowchart 175 of FIG. 4 and timing diagrams of FIGS. 5-6. Initially, the clock divider counter 104 is loaded with the most significant bits (MSBs) of the divider value from the divider counter store 102 (Block 177) in response to the load signal. At the rising edge of each clock cycle, the clock divider counter 104 decrements the number stored therein by one (Block 179).

When the least significant bit (LSB) BitO of the divider value is equal to zero (Odd), the divider value is an even number (Block 181), and the NOR gate 112 serves to compare the current value contained in the clock divider counter 104 to a value of one (Block 183), and asserts its output if the current value contained in the clock divider counter 104 is equal to one (Block 185). This results in the OR gate 114 asserting its output and thus the assertion of the end count signal as high (Block 191). Where the current value contained in the clock divider counter 104 is not one, the clock divider counter value is decremented again (Block 179) in response to the clock signal, and the method restarts from there.

Where the LSB of the divider value is equal to one, the divider value is an odd number (Block 181) and where the toggle signal is equal to one (Block 184), the NOR gate 110 serves to compare the current value contained in the clock divider counter 104 to a value of zero (Block 187), and asserts its output if the current value contained in the clock divider counter 104 is equal to the value of zero (Block 189). This results in the OR gate 114 asserting its output and thus the assertion of the end count signal as high (Block 191). Where the current value contained in the clock divider counter 104 is not zero, the clock divider counter value is decremented again (Block 179) in response to the clock signal, and the method restarts from there.

After generation of the end count signal (Block 191), the toggle signal is transitioned at the falling edge of the end count signal (Block 193), which occurs when load is asserted because counter 104 returns to the divider value number. It is noted that the load signal is asserted at the same falling edge of the end count signal (Block 195). The assertion of the load signal causes the reloading of the clock divider counter with the MSBs of the divider value (Block 177), and the method restarts from there.

The transitioning of the toggle signal as described above results in the generation of the toggle signal as running from falling edge of one pulse of the end count signal to the falling edge of the next pulse of the end count signal, as shown in FIGS. 2A, and FIGS. 5-6. The use of this end count signal in the generation of the output of the clock signal as divided by the divider value will be described below, but first, the structure of the clock divider 150 (also included in circuit 56) will be discussed.

The clock divider 150 includes a flip flop 152 that is clocked by the clock signal, receives the toggle signal as input, and serves to output a version of the toggle signal toggle_d1 that is delayed by a full clock signal. A latch 154 is clocked by an inverse of the clock signal, also receives the toggle signal as input, and serves to output a version of the toggle signal toggle_h1 that is delayed by a half clock signal.

The AND gate 156 receives the toggle signal and the toggle_d1 signal as input and provides output to the multiplexer 158, which receives the toggle signal as its other input. The output of the multiplexer 158 is selected as a function of the LSB (odd) of the divider value. The signal output by the multiplexer 158 is labeled as EN0. The multiplexer 160 receives as input the EN0 signal, as well as the toggle_h1 signal, which is also labeled as EN1. The output of the multiplexer 160 is selected as a function of the clock signal, and the signal output by the multiplexer 160 is the clock output signal, which is the clock signal divided by the divider value.

In operation, where the divider value is even, the toggle signal is connected through to the output of the multiplexer 158 as the EN0 signal. The EN0 signal is connected through to the output of the multiplexer 160 as the clkout signal when the clock signal is low. The EN1 signal is connected through to the output of the multiplexer 160 as the clkout signal when the clock signal is high. Resultingly, the pulse width of the clkout signal equals that of the toggle signal.

Where the divider value is odd, the result of a logical AND between the toggle signal and the toggle_d1 signal is connected through to the output of the multiplexer 158 as the EN0 signal. The EN0 signal is connected through to the output of the multiplexer 160 as the clkout signal when the clock signal is low. The EN1 signal is connected through to the output of the multiplexer 160 as the clkout signal when the clock signal is high. Resultingly, the pulse width of the clkout signal equals that of the clock signal, aligning the toggle signal to generate a 50/50 duty cycle clkout signal.

The design of divider block 56 described above allows for the division by both even and odd integers, and generates the clkout signal with a 50/50 duty cycle in a glitch free fashion. However, as should be appreciated, in some cases a divider block 54 capable of division by fractional numbers (such as an integer indivisible by two without a remainder) may be desired. Such a design will now be described.

With reference to FIG. 7, a counter circuit 200 for use in a divider block 54 capable of division by a fractional number is now described.

The counter circuit 200 includes a divider counter 212, which is clocked by the clock signal, is reloaded based on the end count signal, and receives as input the divider value. The output of the divider counter 212 is coupled to the comparison block 222.

An AND gate 214 receives as input an inverted version of the toggle signal, a signal indicating that a half clock division is to be performed, and a toggle1 signal (while generation of the toggle1 signal will be described below, it should be understood that the toggle1 signal is asserted from a falling edge of one pulse of the toggle signal to a falling edge of a next pulse of the toggle signal). An AND gate 216 receives as input the LSB of the divider value and the toggle signal. An OR gate 218 receives as input the outputs from the AND gates 214 and 216, and provides output to a selection terminal of a multiplexer 220. The inputs of the multiplexer 220 are coupled to a reference value of one and a reference value of zero, and the output of the multiplexer 220 is coupled to the comparison block 222. The comparison block 222 generates the end count signal. The circuit formed by the multiplexer 220 and the comparison block 222 is the same as the circuit formed by the NOR gates 110 and 112, and the OR gate 114.

Operation of the counter circuit 200 will now be described with reference to FIGS. 9-10. Generally speaking, where a signal indicating that a half clock division is to be performed is not asserted, the counter circuit 200 provides the same output as the counter circuit 100 of FIG. 2 given the same inputs.

As shown in the flowchart 265 of FIG. 9, initially, the clock divider counter 212 is loaded with the most significant bits (MSBs) of the divider value (Block 267). At the rising edge of each clock cycle, the clock divider counter 212 decrements the number store therein by one (Block 269).

Where the clock divider counter value is even (Block 271)—as in where, when represented as a mixed number, the integer portion is even—where the toggle signal is low, where the toggle1 signal is high (thus the end count counter value is two), and where the half count signal is high (Block 273), AND gate 214 asserts its output, which in turn is passed by the OR gate 218 to the selection terminal of the multiplexer 220, causing it to select the zero at its second input. The comparison block 222 then compares the divider counter value to the zero from the multiplexer 220 (Block 283), which asserts the end count signal where the divider counter value is equal to zero (Block 285 and Block 287). Where the divider counter value was not zero, the clock divider counter value is decremented (Block 269), and the method continues from there.

In other scenarios (i.e. toggle is low, toggle1 is low, and the clock divider counter value is even, and thus end count counter is zero; toggle is high, toggle1 is low, and the clock divider is even, and thus end counter counter is one; toggle is high, toggle1 is high, and the clock divider is even, and thus end counter counter is three), (Block 273), then AND gate 214 deasserts its output. The output of AND gate 216 is deasserted where either toggle is low or the clock divider counter value is odd. In turn, OR gate 218 deasserts its output, causing multiplexer 220 to select the one at its first input. The comparison block 222 then compares the divider counter value to the one from the multiplexer 220 (Block 275), which asserts the end count signal where the divider counter value is equal to one (Block 277 and Block 287). Where the divider counter value was not one, the clock divider counter value is decremented (Block 269), and the method continues from there.

Where the clock divider counter value is odd (Block 271)—as in where, when represented as a mixed number, the integer portion is odd—and where the toggle signal is high AND gate 216 asserts its output, which in turn is passed by the OR gate 218 to the selection terminal of the multiplexer 220, which selects the zero at its second input. The comparison block 222 then compares the divider counter value with the zero from the multiplexer 220 (Block 283), and asserts the end count signal where the divider counter value is equal to zero (Block 285 and 287). Where the divider counter value was not zero, the clock divider counter value is decremented (Block 269), and the method continues from there.

If the toggle signal was not high, then AND gate 216 deasserts its output. In that case, output of the OR gate 218 is controlled by output of the AND gate 214, which serves to add an extra count during half clock division. To that end, the AND gate 214 is deasserted where toggle is high and the clock divider counter value is odd (Block 279), and where toggle is low, toggle1 is low (end count counter is zero), and the half clock signal is low (Block 281). The AND gate 214 is asserted where toggle is low and toggle1 is high (end count counter is two) and the half clock signal is high (Block 273).

Where neither AND gate 214 nor AND gate 216 asserts its output, OR gate 218 deasserts its output, causing multiplexer 220 to select the one at its first input. The comparison block 222 then compares the divider counter value to the one from the multiplexer 220 (Block 275), which asserts the end count signal where the divider counter value is equal to one (Block 277 and Block 287). Where the divider counter value was not one, the clock divider counter value is decremented (Block 269), and the method continues from there.

After generation of the end count signal (Block 287), the toggle signal is transitioned at the falling edge of the end count signal (Block 289), and the load signal is asserted at the same falling edge of the end count signal (Block 291). The assertion of the load signal causes the reloading of the clock divider counter with the MSBs of the divider value (Block 267), and the method restarts from there.

The transitioning of the toggle signal as described above results in the generation of the toggle signal as running from falling edge of one pulse of the end count signal to the falling edge of the next pulse of the end count signal, as shown in FIG. 10. The use of this end count signal in the generation of the output of the clock signal as divided by the divider value will be described below, but first, the structure of the clock divider 250 will be discussed.

With reference to FIG. 8, the clock divider 250 includes a multiplexer 253 receiving as input the toggle signal and an inverted version of the toggle signal, and being controlled by the end count signal. The multiplexer 253 provides its output to a flip flop 254. The flip flop 254 asserts the toggle signal at its output. A flip flop 256 receives as input the toggle signal, and asserts the clock signal delayed version of the toggle signal toggle_d1 at its output. The AND gate 262 receives as input the toggle signal and the toggle_d1 signal, and provides output as an input to the multiplexer 268, which receives the toggle signal as its other input, and the LSB of the divider value at its selection terminal.

The AND gate 258 receives the toggle signal and the end count as its input, provides its output to control multiplexer 259, which provides it output to flip flop 260 as input thereto, which in turn provides its output and an inverted version thereof to the multiplexer 259 as inputs. The output of the flip flop 260 is coupled to the selection terminal of the multiplexer 270. The AND gate 264 receives as input the toggle signal and the toggle_d1 signal, and provides its output to the multiplexer 270 as an input thereof. The OR gate 266 receives the toggle signal and the toggle_d1 signal as its input, and provides its output to the multiplexer 270 as another input thereof.

The multiplexer 272 receives the outputs of the multiplexers 268 and 270 as its inputs, and receives the half clock signal at its selection terminal. The multiplexer 272 asserts EN0 at its output.

The latch 274 receives the toggle signal at its input, is enabled by the clock signal, and asserts the EN1 signal at its output. The multiplexer 276 receives the EN0 and EN1 signals as its input and the clock signal at its selection terminal, and asserts the clkout signal at its output.

Generally speaking, where the signal indicating that a half clock division is to be performed is not asserted, the counter circuit 250 provides the same output as the counter circuit 150 of FIG. 3 given the same inputs.

In operation, the clock divider serves to assert the EN0 signal when toggle1 is deasserted, toggle is asserted, and toggle_d1 is asserted, or when toggle1 is asserted and either of toggle or toggle_d1 is asserted. The EN0 signal is connected through to the output of the multiplexer 276 as the clkout signal when the clock signal is low.

Due to enabling of the latch 274 by an inverted version of the clock signal, the EN1 signal is asserted at the falling edge of the clock signal, and is connected through to the output of the multiplexer 276 as the clkout signal when the clock signal is high. As can be seen from the timing diagram of FIG. 10, a true 50/50 duty cycle is not achieved by the divider block 56 when making a fractional division as described above, although the resulting clkout signal is close to a 50/50 duty cycle and is still suitable for use in a variety of applications.

As should be appreciated, the method described above is suitable for other fractional divides other than one half. For example, fraction divides of one quarter or one eighth may be made. In that case, the multiplexer 272 receives the outputs of the multiplexers 268 and 270 as its inputs, and receives a fractional divide signal at its selection terminal. The multiplexer 272 asserts the EN0 at its output. By changing the logic used in generating EN0, for example by adding delay to the inputs or selection terminal of the multiplexer 272, the duty cycle of clkout can be modified.

With reference to FIG. 11, a further embodiment of a divider block 56 capable of making a fractional divide is now described. Here, the divider block includes two multiplexers 380 and 382, that each receive inputs from a state machine. The multiplexer 380 provides its output to the flip flop 384, while the multiplexer 382 provides its output to the flip flop 386. The flip flops 384 and 386 are clocked by the clock signal. The flip flop 384 provides its output to the AND gate 390 as the EN0 signal, while the flip flop 386 provides it output to the flip flop 391 as the EN1 signal. The flip flop 391 provides its output to the OR gate 392, which in turn provides its output to the multiplexer 394 as an input. The output of the AND gate 390 is also fed to the multiplexer 394 as an input. The multiplexer 394 has the clock signal coupled to its selection signal.

It should be understood that the AND gate 390 (which receives a test signal as input) and OR gate 392 are optional and there for testing purposes, and need not be present. Thus, the output of the multiplexer 384 may be fed to the multiplexer 394 as input, and the output of the flip flop 391 may be fed to the multiplexer 394 as input.

Operation of this divider block 56 proceeds with generating the EN0 and EN1 signals as described above.

The methods and techniques descried in detail above for dividing by a fractional number will now be described more generally with reference to FIGS. 12-13. With reference to the flowchart 300 of FIG. 12, initially, the clock divider counter is loaded with the MSBs of the divider value (Block 302), and the clock divider counter is then decremented (Block 304).

Where the divider value is a mixed number having an even integer portion, the clock divider value (after each decrement of the clock divider counter value) is compared to one (Block 308). Where the clock divider value is equal to one (Block 310), the end count signal is then asserted (Block 330), toggle is transitioned at a falling edge of end count (Block 332), the load signal is asserted (Block 334), and then the clock divider counter is reloaded with the

MSBs off the divider value (Block 302). Where the clock divider value is not equal to one (Block 310), the clock divider value is decremented (Block 304).

However, where the fractional portion of the divider value is one half (Block 314), every four assertions of the end count signal (referred to as output cycles in the flowchart 300), the clock divider value is compared to zero (Block 316), and where end clock divider value is equal to zero (Block 317), the method proceeds with asserting end count as described above.

Where the fractional portion of the divider value is one quarter (Block 318), every eight assertions of the end count signal, the clock divider value is also compared to zero (Block 320). Where the fractional portion of the divider value is one eighth (Block 322), every sixteen assertions of the end count signal, the clock divider value is also compared to zero (Block 324). Thus it follows that where the fractional portion of the divider value is N, every 2*N assertions of the end count signal (Block 326), the clock divider value is also compared to zero (Block 328).

Where the divider value is a mixed number having an odd integer portion, the clock divider value (after each decrement of the clock divider counter value) is compared to zero every other output cycle (Block 312), and where it is equal to zero (Block 313), the method proceeds to Block 330 and end count is asserted as described above. On the alternate output cycles, the clock divider value is compared to one (Block 335), and where it is equal to one (Block 336), the method proceeds to Block 330 and end count is asserted as described above.

The above is exampled and illustrated in the timing diagram shown in FIG. 13.

Although the preceding description has been described herein with reference to particular means, materials and embodiments, it is not intended to be limited to the particulars disclosed herein; rather, it extends to all functionally equivalent structures, methods, and uses, such as are within the scope of the appended claims. 

1. A circuit, comprising: a counter circuit comprising: a clock divider counter configured to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal, logic configured to: compare a value contained in the divider counter to a reference value, and generate an end count signal as a function of the value contained in the divider counter matching the reference value, wherein the reference value is set to zero as a function of a least significant bit of the divider value and assertion of a toggle signal, wherein the reference value is also set to zero as a function of the least significant bit of the divider value, deassertion of the toggle signal, and assertion of a second toggle signal; wherein the clock divider counter is also configured to be reloaded with the most significant bits of the divider value as a function of the end count signal; and a clock divider configured to: transition a first toggle signal at a same edge of each pulse of the end count signal, transition a second toggle signal at a same edge of every other pulse of the end count signal, and generate a divided version of the clock signal as a function of the first and second toggle signals.
 2. The circuit of claim 1, wherein the clock divider comprises a first multiplexer configured to generate a first output signal by multiplexing the first toggle signal and a signal representing a result of a logical AND between the first toggle signal and a delayed version of the first toggle signal as a function of the least significant bit of the divider value.
 3. The circuit of claim 2, wherein the clock divider further comprises: a second multiplexer configured to generate a second output signal by multiplexing the signal representing a result of a logical AND between the first toggle signal and the delayed version of the first toggle signal and a signal representing a result of a logical OR between the first toggle signal and the delayed version of the first toggle signal as a function of the second toggle signal; a third multiplexer configured to generate a third output signal by multiplexing the first and second output signals as a function of a half clock division signal, the half clock division signal being asserted when the first toggle signal is deasserted and the second toggle signal is asserted; and a fourth multiplexer configured to generate the divided version of the clock signal by multiplexing the third output signal and a half clock delayed version of the first toggle signal as a function of the clock signal.
 4. The circuit of claim 3, wherein the clock divider further comprises: a first AND gate configured to receive the first toggle signal and the delayed version of the first toggle signal as inputs and to provide output to the first multiplexer; a latch configured to latch the first toggle signal to the fourth multiplexer as a function of the clock signal; a fifth multiplexer configured to generate a fourth output signal by multiplexing the first toggle signal and an inverse of the first toggle signal as a function of the end count signal; a first flip flop configured to receive as input the fourth output signal and to provide output of the first toggle signal; a second flip flop configured to receive as input the first toggle signal and to provide output to the first AND gate; a third AND gate configured to receive as input the first toggle signal and the end count signal; a sixth multiplexer configured to generate a fifth output signal by multiplexing the second toggle signal and an inverse of the second toggle signal as a function of output of the third AND gate; and a third flip flop configured to receive as input the fifth output signal and to generate the second toggle signal as output.
 5. The circuit of claim 4, wherein the clock divider further comprises a second AND gate configured to receive the first toggle signal and the delayed version of the first toggle signal as inputs and to provide output to the second multiplexer.
 6. The circuit of claim 4, wherein the clock divider further comprises a first OR gate configured to receive as input the first toggle signal and the delayed version of the toggle signal, and to provide output to the second multiplexer.
 7. The circuit of claim 1, wherein the clock divider counter and logic are embodied within a state machine.
 8. The circuit of claim 1, wherein the logic of the counter circuit comprises: a first AND gate configured to receive as input the first toggle signal, the second toggle signal, and the half clock division signal; a second AND gate configured to receive as input the first toggle signal and the least significant bit of the divider value; a first OR gate configured to receive input from the first and second AND gates and to generate a selection signal; a first multiplexer configured to generate the reference value by multiplexing a value of 1 and a value of 0 as a function of the selection signal; a comparison circuit configured to compare the value contained in the divider counter to the reference value and to generate the end count signal as a function thereof.
 9. The circuit of claim 11, wherein the counter circuit and clock divider form a block; wherein the circuit comprises a plurality of division blocks, with each division block having a copy of the block but with a different divider value; and wherein the clock signal is a predetermined fraction of a phase locked loop's clock signal.
 10. The circuit of claim 9, wherein the predetermined fraction is one half.
 11. The circuit of claim 9, wherein the clock signal is less than 1 GHz.
 12. The circuit of claim 9, wherein the plurality of division blocks is at least ten division blocks.
 13. A method, comprising: loading a clock divider counter with most significant bits of a divider value; decrementing the clock divider counter at a same edge of each pulse of a clock signal; comparing a value contained in the divider counter to a reference value and generate an end count signal as a function of the value contained in the divider counter matching the reference value, using logic circuitry; wherein the divider value is even, the reference value is set to 1; wherein the divider value is odd, the reference value is set to 1, except for every other assertion of the end count signal where the divider value is set to 0; transitioning a toggle signal at a same edge of each pulse of the end count signal, reloading the clock divider counter with the most significant bits of the divider value as a function of the end count signal; and generating a divided version of the clock signal as a function of the toggle signal, using the clock divider.
 14. The method of claim 13, wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ½; wherein: the integer part of the divider value is even, the reference value is set to 1, except for every 4th assertion of the end count signal, where the divider value is set to 0; and the integer part of the divider value is odd, the reference value is set to 1, except for: every other assertion of the end count signal, where the divider value is set to 0; and every 4th assertion of the end count signal, where the divider value is set to
 0. 15. The method of claim 13, wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ¼; wherein: the integer part of the divider value is even, the reference value is set to 1, except for: every 4th assertion of the end count signal, where the divider value is set to 0; and every 8th assertion of the end count signal, where the divider value is set to 0; and the integer part of the divider value is odd, the reference value is set to 1, except for: every other assertion of the end count signal, where the divider value is set to 0; every 4th assertion of the end count signal, where the divider value is set to 0; and every 8th assertion of the end count signal, where the divider is set to
 0. 16. The method of claim 13, wherein the divider value is a mixed number having an integer part and a fractional part, with the fractional part being ⅛; wherein: the integer part of the divider value is even, the reference value is set to 1, except for: every 4th assertion of the end count signal, where the divider value is set to 0; every 8th assertion of the end count signal, where the divider value is set to 0; and every 16th assertion of the end count signal, where the divider value is set to 0; and the integer part of the divider value is odd, the reference value is set to 1, except for: every other assertion of the end count signal, where the divider value is set to 0; every 4th assertion of the end count signal, where the divider value is set to 0; every 8th assertion of the end count signal, where the divider is set to 0; and every 16th assertion of the end count signal, where the divider value is set to
 0. 